1. Field of the Invention
The present invention relates to a test method for a semiconductor device, and more particularly to a failure test method for a split gate flash memory.
2. Description of the Related Art
Flash memories can program, read and erase data for multiple times, and data stored therein can be maintained even if the power applied thereto is off. Therefore, flash memories have become the major non-volatile memory widely used in personal computers and electronic equipment.
A typical flash memory comprises a floating gate and a control gate. The floating gate and the control gate are separated by a dielectric layer. The floating gate and the substrate are separated by a tunnel oxide layer. During data erasing in the flash memory, since the amount of electrons ejected from the floating gate is difficult to control, the floating gate would over-eject the electrons with positive charges, called over-erasing. If the over-erasing is so serious that the channel under the floating gate is turned on when power is not applied on the control gate, the data stored in the memory will be erroneously judged. In order to solve the over-erasing issue, split gate flash memories are introduced, for example, in U.S. Pat. No. 6,584,018 and U.S. Pat. No. 6,355,524.
FIG. 1 is a schematic cross-sectional view showing a conventional split gate flash memory cell. Referring to FIG. 1, the split gate flash memory comprises a tunnel oxide layer 102, a floating gate 104, an inter-gate dielectric layer 106 and a control gate 108, sequentially stacked over a substrate 100, and also a select gate 112 on sidewalls of the floating gate 104 and the control gate 108 where they are separated by a dielectric layer 110. The select gate 112 and the substrate 100 are separated by a select gate dielectric layer 114. The source region 116 is formed in the substrate 100 and adjacent to a side of the floating gate 104 and the control gate 108. The drain region 118 is formed in the substrate 100 and adjacent to the select gate 112, i.e. the word line. The drain region 118 is electrically connected to the bit line 122 through the contact 120.
A disadvantage of this split gate flash memory cell is its vulnerability to defects, such as particles. Especially, defects or particles between the contact 120 and the select gate 112, i.e. the word line, would lead to a short circuit in the word line-bit line, bringing the whole sector to a breakdown. The short circuit in the word line-bit line is a main killer, which crashes the programming/erasing function of the memory. One single defect or particle may render the whole chip irreparable.
Generally, in the failure analysis of flash memories, DC analyzing equipment is used to locate defects. By detecting hot spots or light spots, defect locations can be identified. However, this method can only locate the defects, but cannot precisely identify the address of the word line-bit line short circuit, i.e. the main killer. Moreover, the conventional method requires a complicated analyzing process, and cannot easily, efficiently locate the defects.